1. Field of the Invention
The present invention relates to a clock signal generation circuit in a semiconductor chip and more particularly to a reset signal generation circuit for generating internal clock signals in a chip.
2. Description of Related Art
It takes a little time for a stable clock signal to be generated after a chip is powered and an oscillation circuit is activated. This period of time is called an oscillation-stability time. During the oscillation-stability time, reset signals are generated not to let the chip operate. Because not only power supply voltage is not sufficiently ensured, but also frequency of a clock signal is not stabilized during the oscillation-stability time, stability of circuit operation cannot be guaranteed, so the chip is prevented from operating using the reset signal.
FIG. 1 is a block diagram of a related art reset signal generation circuit.
Oscillator 102 performs oscillating operation in response to an incoming external clock signal, CLK_EXT.
Clock generator 104 receives an oscillation signal from the oscillator 102 and an external reset signal, /RST_EXT, and generates an internal clock signal, CLK_INT, of a predetermined frequency. The external reset signal, /RST_EXT, has an initial value of a low level and is provided as an internal reset signal, /RST_INT, to prevent the remaining elements other than the clock generator 104 from being activated.
FIG. 2 is a timing chart for showing an operating characteristic of the above related art reset signal generation circuit.
Once the chip is powered and a level of power voltage, VCC, starts to increase, oscillation of the internal clock signal, CLK_INT, starts. The frequency of the internal clock signal, CLK_INT, is not stable because the level of the power voltage, VCC, is not sufficient. At this time, the internal reset signal, /RST_INT, has a low level, so other elements in the chip do not operate.
Once the power voltage level is sufficiently ensured during the oscillation-stability time and the oscillation-stability time has been passed, the internal reset signal, /RST_INT, goes to a high level. Since the frequency of the internal clock signal, CLK_INT, is satisfactorily stable at this time, the chip becomes to operate in normal.
However, the related art reset signal generation circuit should detect a settling time of the oscillator in advance and ensure a corresponding oscillation-stability time. Such fixed oscillation-stability time may delay the start of operation of the chip unnecessarily or may not ensure an enough oscillation-stability time because the circuit cannot reflect the condition when the operating characteristic of the oscillator deteriorates.
Moreover, since the operating characteristic of the oscillator generating the oscillation signal using the external clock signal, CLK_EXT, depends upon the external clock signal, CLK_EXT, a characteristic of the oscillation signal generated by the oscillator 102 is also unstable if the external clock signal, CLK_EXT, becomes unstable.